Core Values(TM) Product Family
Our Core Values(TM) products (PDF) are delivered with a Verilog 2001 testbench including the final sign-off test set. No PLI or C are involved.
Each core is synthesized using FPGA vendor-specific tools to make sure that there are no warnings and that timing is met*.
Deep media domain knowledge and extensive ASIC and FPGA design and verification experience allow video-cores.com to deliver the highest quality Intellectual Property (IP) for consumer electronics and professional applications.
The expertise of our principals ranges from Standard-definition (SD) and High-definition (HD) video capture and compression to Digital Television (DTV) de-compression and display including all steps and functional blocks in between.
video-cores.com follows the strictest coding style guidelines for its cores including (but not limited to):
- Detailed documentation header with licensing information
- Comments in every coded line
- Labels for 'begin' and comments for 'end'
- Meaningful register and wire names
- Indenting code to increase readability
- Limiting lines to 72 characters
- Including 'begin-end' for all 'initial','always','case','if-else' blocks
- Only including 'initial' blocks for testbenches
- Resetting every flop
- Not including latches or tri-states
- Fully-synchronous state machines
Best-in-industry coding guidelines are the result of many years of disciplined learning by our principals checking verilog code using leading-edge tools such as Synopsys LEDA®, Atrenta Sypglass®, Mentor DesignAnalyst(TM) and verifying code for large (up to six million gates) consumer electronics chips.
All IP is verified through a combination of directed and pseudo-random tests. The directed tests show first all error conditions then normal functionality. Pseudo-random testing allows for all corners of the design to be explored.
Cores are delivered via e-mail, FTP or in a CD-ROM via signature-required FedEx delivery.* FPGA tools are allowed to place core freely without pin constraints.